View PDSP1883_289119.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PDSP1880 YELLOW PDSP1881 HIGH EFFICIENCY RED PDSP1882 GREEN PDSP1883 HIGH EFFICIENCY GREEN PDSP1884
RED YELLOW 0.180" 8-Character 5x7 Dot Matrix Alphanumeric Programmable DisplayTM
Package Dimensions in Inches (mm)
1.690 (42.93) max. .105 (2.68) .211 (5.36)
0 1 2 3 4 5 6 7
.180 (4.57)
.450 (11.43) max. .090 (2.29) C L .060 (1.52) Ref. .210 (5.33) C L .010 (0.25)
Pin 1 Identifier
C L .100 (2.54) C L
Pin 16 .012 (0.30) typ .300 (7.62)
FEATURES * Eight 0.180" Dot Matrix Characters in Red, Yellow, High Efficiency Red, Green, or High Efficiency Green * Built-in 128 Character ROM, Mask Programmable for Custom Fonts * Readable from 8 Feet (2.5 meters) * Built-in Decoders, Multiplexers and Drivers * Wide Viewing Angle, X Axis 55, Y Axis 65 * Programmable Features: - Individual Flashing Character - Full Display Blinking - Multi-Level Dimming and Blanking - Clear Function - Self Test * Internal or External Clock * End Stackable Dual-In-Line Plastic Package * Read/Write Capability * 16 User Definable Characters
.020 (0.51) Pin #1 .100 -.005 typ. (2.54 -0.13) (Tol. non-cum.) .400 (10.16)
.200 (5.08) .018 (0.46) typ.
.158 (4.01) typ. Pin #15 .225 (5.71)
DESCRIPTION The PDSP1880 (Red), PDSP1881 (Yellow), PDSP1882 (High Efficiency Red), PDSP1883 (Green), and PDSP1884 (High Efficiency Green) are eight digit, 5x7 dot matrix, alphanumeric Programmable Displays. The 0.180 inch high digits are packaged in a rugged, high quality, optically transparent, 0.300 inch lead spacing, 30 pin plastic DIP. The on-board CMOS has a built-in 128 character ROM. The PDSP188X also has a user definable character (UDC) feature, which uses a RAM that permits storage of 16 arbitrary characters, symbols or icons that are software-definable by the user. The character ROM itself is mask programmable and easily modified by the manufacturer to provide specified custom characters. The PDSP188X is designed for standard microprocessor interface techniques, and is fully TTL compatible. The Clock I/O and Clock Select pins allow the user to cascade multiple display modules.
2-107
ESD Warning: Standard precautions for CMOS handling should be observed. Maximum Rating (TA=25C) DC Supply Voltage, VCC to GND (max. voltage with no LEDs on)...................... -0.3 to +7.0 VDC Input Voltage Levels, All Inputs.............................. -0.3 V to VCC+0.3 V Operating Temperature .................-40C to +85C Storage Temperature....................-40C to +100C Relative Humidity (non-condensing)................85% Operating Voltage, VCC to GND (Max. voltage with 20 dots/digits on)............5.5V Maximum Solder Temperature ...................... 260C (0.063" below the seating plane, t<5 sec.) ESD Protection at 1.5 K, 100 pF................................... VZ=4 KV (each pin) Figure 1. Enlarged character format Dimensions in inches (mm)
0.098 (2.49) C1 C2 C3 C4 C5 R1 0.028 (0.71) Typ. R2 R3 R4 R5 R6 0.01 (0.254) Typ. R7 0.178 (4.52)
Switching Specifications (over operating temperature range and VCC=4.5 V) Symbol Tacc Tacc Tacs Tce Tce Tach Tcer Tces Tces Tceh Tw Twd Tdh Tr Trd Tdf Description Display Access Time-Write Display Access Time-Read Address Setup Time to CE Chip Enable Active Time-Write Chip Enable Active Time-Read Address Hold Time to CE Chip Enable Recovery Time Chip Enable Active Prior to Rising Edge-Write Chip Enable Hold Prior to Rising Edge-Read Chip Enable Hold to Rising Edge of Read/Write Signal Write Active Time Data Valid Prior to Rising Edge of Write Signal Data Write Time Chip Enable Active Prior to Valid Data Read Active Prior to Valid Data Read Data Float Delay Reset Active Time Min. 210 230 10 140 160 20 60 140 160 0 100 50 20 160 95 10 300 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
0.022 (0.56) Typ.
Trc Figure 2. Write Cycle timing diagram Tacc A0-A3 FL Tach Tacs CE Tces Tw WR Twd D0-D7 Tdh Tceh Tce
Tacs Tcer
PDSP1880/1881/1882/1883/1884
2-108
Figure 3. Read Cycle timing diagram Tacc A0-A3 FL Tacs CE Tces Tr RD Trd D0-D7 Tdf Tceh Tach Tce Tcer Tacs
Character Set
D0 D1 D2 D3 D7 D6 D5 D4 HEX ASCII CODE L L L L 0 L L L L 0 H L L L 1 L H L L 2 H H L L 3 L L H L 4 H L H L 5 L H H L 6 H H H L 7 L L L H 8 H L L H 9 L H L H A H H L H B L L H H C H L H H D L H H H E H H H H F
L
L
L
H
1
L
L
H
L
2
L
L
H
H
3
L
H
L
L
4
L
H
L
H
5
L
H
H
L
6
L
H
H
H
7
H
X
X
X
8
UDC UDC 0 1
UDC UDC UDC UDC 2 3 4 5
UDC UDC 6 7
UDC UDC 8 9
UDC UDC 10 11
UDC 12
UDC 13
UDC 14
UDC 15
Notes: 1. Upon power up, device will initialize in a random state 2. X=Don't care.
PDSP1880/1881/1882/1883/1884
2-109
Optical Characteristics at 25C VCC=5.0 V at Full Brightness Red PDSP1880 Description Luminous Intensity Peak Wavelength Dominant Wavelength Yellow PDSP1881 Description Luminous Intensity Peak Wavelength Dominant Wavelength High Efficiency Red PDSP1882 Description Luminous Intensity Peak Wavelength Dominant Wavelength Green PDSP1883 Description Luminous Intensity Peak Wavelength Dominant Wavelength High Efficiency Green PDSP1884 Description Luminous Intensity Peak Wavelength Dominant Wavelength Symbol IV (peak) (d) Min. 125 Typ. 500 568 574 Max. Units cd/dot nm nm Symbol IV (peak) (d) Min. 125 Typ. 275 565 570 Max. Units cd/dot nm nm Symbol IV (peak) (d) Min. 125 Typ. 350 630 626 Max. Units cd/dot nm nm Symbol IV (peak) (d) Min. 125 Typ. 205 583 585 Max. Units cd/dot nm nm Symbol IV (peak) (d) Min. 70 Typ. 125 660 639 Max. Units cd/dot nm nm
PDSP1880/1881/1882/1883/1884
2-110
DC Electrical Characteristics at 25C Parameter Limits
Min. Typ. Max. Units
Conditions
VCC ICC Blank lCC 12 dots/digit on (1, 2) lCC 20 dots/digit on (1, 2) lILP (with pull-up) Input Leakage lIL (no pull-up) Input Leakage VIH Input Voltage High VIL Input Voltage Low VOL (D0 to D7) Output Voltage Low VOL (CLK) Output Voltage Low VOH Output Voltage High
4.5
5.0 0.65 200 300
5.5 1.0 255 370 -5 +1 VCC +0.3
V mA mA mA A A V V VCC=5 V, VIN=5 V VCC=5 V, "V" in all 8 digits VCC=5 V, "#" in all 8 digits VCC=5 V, VIN=0 V to VCC (WR, CE, FL, RST, RD, CLKSEL) VCC=5 V, VIN=5 V (CLK, A0-A3, D0-D7) VCC=4.5 V to 5.5 V VCC=4.5 V to 5.5 V VCC=4.5 V, IOL=1.6 mA VCC=4.5 V, IOL=40 A VCC=4.5 V, IOH=40 A
-18 -1 2.0 Gnd -0.3
-11
0.4 0.4 2.4 60 28 125 0.98 57.34 256 2.0 81.14 362.5 2.83 2.40 500 500
V V V C/W KHz Hz Hz pF nsec nsec
JC Thermal Resistance, Junction to Case
Clock I/O Frequency FM, Digit Multiplex Frequency Blinking Rate Clock I/O Bus Loading Clock Out Rise Time Clock Out Fall Time
VCC=4.5 V to 5.5 V VCC=4.5 V to 5.5 V
VCC=4.5 V, VOH=2.4 V VCC=4.5 V, VOH=0.4 V
Notes: 1. ICC is an average value. 2. ICC is measured with the display at full brightness. Peak ICC=28/15 ICC average (# displayed).
Recommended Operating Conditions (TA=-40C to +85C) Parameter Supply Voltage Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Symbol VCC VIL VIH VOL VOH 2.4 2.0 0.4 Min. 4.5 Max. 5.5 0.8 Units V V V V V
PDSP1880/1881/1882/1883/1884
2-111
Figure 4. Top view
Pin #
Name Clock In/Out Write
Symbol CLK WR
Definition Inputs or outputs clock as determined by CLS. Writes data into display when WR=0. Note CE=0 to enable write cycle. Enables display's write and read cycles when CE=0. Positive power supply input. Analog ground for LED drivers No connection Logic ground for digital circuitry Reads data from display when RD=0. Also CE=0 . Least significant data bit. Second data bit. No connections
0
1
2
3 4 5 6 7
12 13
14 Pin Assignments Pin # 1 Name Reset Symbol RST Definition Initializes display: clears Character RAM (20 H), Flash RAM (00 H), control word (00 H), and resets internal counters. UDC Address Register and UDC RAM unaffected. Accesses Flash RAM. Address inputs A0-A2 select digit address while data bit D0 sets (D0=1) or resets (D0=0) Flash bit, A3 and A4 ignored. A0-A2 select specific digits. See Table 1. Same as A0 Same as A0 A3 and A4 access parts of memory together with Flash pin. See Table 1. No connections A4 CLS Same as A3 Selects internal or external clock source. CLS=1 selects internal clock (master), CLS=0 selects external clock (slave operation). 15 16 17 18 19 20 21 22- 24 25 26 27 28 29 30
Chip Enable Positive supply Supply GND
CE VCC GNDsup NC
Logic GND Read Data bit zero Data bit one No pins Data bit two Data bit three Data bit four Data bit five Data bit six Data bit seven
GNDlog RD D0 D1
2
Flash
FL
3 4 5 6
Addr. input
A0 A1 A2
Addr. input No pins Addr. input Clock Select
A3
D2 D3 D4 D5 D6 D7
Third data bit. Fourth data bit. Fifth data bit. Sixth data bit. Seventh data bit. Most significant data bit. * Determine the correct address for each display. * Use CE from an adrress decoder to select the correct display.
7-9 10 11
Figure 5. Cascading displays
RD WR FL RST VCC RD WR FL RST CLK I/O CLKSEL Display D0-D7 A0-A4
Data I/O Address
RD WR Up to14 More Displays in between
FL
RST CLK I/O CLKSEL Display
* Use CE from an adrress decoder to select the correct display. * Select one of the Displays to provide the Clock for the other displays. Connect CLKSEL to VCC for this display. * Tie CLKSEL to ground on other displays. * Use RST to synchronize the blinking between the displays.
PDSP1880/1881/1882/1883/1884
CE
D0-D7 A0-A4
CE
A6 A7 A8 A9
0 Address Decoder Address Decode Chip 1 to 14 15
The PDSP188X is designed to drive up to 16 other PDSP188Xs with input loading of 15 pF each. General requirements for cascading 16 displays together:
2-112
Figure 6. Block diagram
OSC
/32 Counter
/7 Counter
Row Drivers
8 Digit Display
Column Drivers
/128 Counter
/3 Counter
Character RAM Decode
Character RAM
D Latch Holding Register
ROM 64 Word Decode
ROM
5
Column Latch S M l a a s t 25 v e e r
25
Cursor Controls and Display MUX
Character Decode 16 for Display
5
16 Data Bus 4 UDC Address Register 4 Character Decode
(Read/Write)
UDC RAM
Self Test
Control Word Register
Flash RAM
Functional Description The display's user interface is organized into five memory areas. They are accessed using the Flash Input, FL, and address lines, A3 and A4. All the listed RAMs and Registers may be read or written through the data bus. See Table 1. Each input pin is described in Pin Definitions. The five basic memory areas are: Character RAM Stores either ASCII (Katakana) character data or an UDC RAM address 1 x 8 RAM which stores Flash data Stores dot pattern for custom characters Provides address to UDC RAM when user is writing or reading a custom character
Control Word Register
Enables adjustment of display brightness, flash individual char-acters, blink, self test or clearing the display.
RST can be used to initialize display operation upon power up or during normal operation. When activated, RST will clear the Flash RAM and Control Word Register (00H) and reset the internal counter. All eight display memory locations will be set to 20H to show blanks in all digits. FL pin enables access to the Flash RAM. The Flash RAM will set (D0=1) or reset (D0=0) flashing of the character addressed by A0-A2. The 1 x 8 bit Control Word Register is loaded with attribute data if A3=0. The Control Word Logic decodes attribute data for proper implementation. Character ROM is designed for 128 ASCII characters. The ROM is Mask Programmable for custom fonts. The Clock Source could either be the internal oscillator (CLKSEL=1) of the device or an external clock (CLKSEL=0) could be an input from another HDSP211X display for the
Flash RAM User-Defined Character RAM (UDC RAM) User-Defined Address Register (UDC Address Register)
PDSP1880/1881/1882/1883/1884
2-113
synchronization of blinking for multiple displays. The Display Multiplexer controls the Row Drivers so no additional logic is required for a display system. The Display has eight digits. Each digit has 35 LEDs clustered into a 5 x 7 dot matrix. Table 1. Memory Selection FLA4A3 0 1 1 X 0 0 X 0 1 Section of Memory Flash RAM UDC Address Register UDC RAM A2-A0 Character Address Don't Care Row Address Data Bits Used D0 D3-D0 D4-D0
FLA4A3 1 1 1 1 1 0
Section of Memory Character RAM Control Word Register
A2-A0 Character Address Don't Care
Theory of Operation Data Bits Used The PDSP188X Programmable Display is designed to work with all D7-D0 major microprocessors. Data entry is via an eight bit parallel bus. Three bits of address route the data to the D7-D0 digit location in the RAM. Standard control signals like proper WR and CE allow the data to be written into the display. D0-D7 data bits are used for both Character RAM and control word data input. A3 acts as the mode selector. If A3=1, character RAM is selected. Then input data bit D7 will determine whether input data bits D0-D6 is ASCII coded data (D7=0) or UDC data (D7=1). See section on UDC Address Register and RAM. For normal operation FL pin should be held high. When FL is held low, Flash RAM is accessed to set character blinking. The seven bit ASCII code is decoded by the Character ROM to generate Column data. Twenty columns worth of data is sent out each display cycle, and it takes fourteen display cycles to write into eight digits. The rows are multiplexed in two sets of seven rows each. The internal timing and control logic synchronizes the turning on of rows and presentation of column data to assure proper display operation. Power Up Sequence Upon power up display will come on at random. Thus the display should be reset on power-up. The reset will clear the Flash RAM, Control Word Register and reset the internal counter. All the digits will show blanks and display brightness level will be 100%. The display must not be accessed until three clock pulses (110 seconds minimum using the internal clock) after the rising edge of the reset line.
PDSP1880/1881/1882/1883/1884
2-114
Microprocessor Interface The interface to a micrprocessor is through the 8-bit data bus (D0-D7), the 4-bit address bus (A0-A3) and control lines FL, CE and WR. To write data (ASCII/Control Word) into the display CE should be held low, address and data signals stable and WR should be brought low. The data is written on the low to high transistion of WR. The Control Word is decoded by the Control Word Decode Logic. Each code has a different function. The code for display brightness changes the duty cycle for the column drivers. The peak LED current stays the same but the average LED current diminishes depending on the intensity level. The character Flash Enable causes 2 Hz coming out of the counter to be ANDED with column drive signal and makes the column driver to cycle at 2 Hz. Thus the character flashes at 2 Hz. The display Blink works the same way as the Flash Enable but causes all twenty column drivers to cycle at 2 Hz thereby making all eight digits to blink at 2 Hz. The Self Test function of the IC consists of two internal routines which exercise major portions of the IC and illuminates all the LEDs. Clear bit clears the character RAM and writes a blank into the display memory. It however does not clear the control word. ASCII Data or Control Word Data can be written into the dis-
RST 1 1
CE 0 0
WR 0 1
RD 1 0
FL 1 1
A4 0 0
A3 0 0
A2
A1
A0
Character Address, Digits 0-7 Character Address, Digits 0-7
Figure 8. UDC Address Register and UDC Character RAM RST 1 1 1 1 CE 0 0 0 0 WR 0 1 0 1 RD 1 0 1 0 FL 1 1 1 1 A4 0 0 0 0 A3 0 0 1 1 A2 A1 A0
Not used for UDC Address Registe Not used for UDC Address Registe A2-A0=Characte Row Address A2-A0=Characte Row Address
UDC Address Register The UDC Address Register is selected by setting FL=1, A4=0, A3=0. It is a 4 bit register and uses data bits, D3-D0 to store the 4 bit address code (D7-D4 are ignored). The address code selects one of 16 UDC RAM locations for cus-
play at this point. For multiple display operation, CLK I/O must be properly selected. CLK I/O will output the internal clock if CLKSEL=1, or will allow input from an external clock if CLKSEL=0. Character RAM The Character RAM is selected when FL, A4 and A3 are set to 1,1,1 during a read or write cycle. The Character RAM is a 8 by 8 bit RAM with each of the eight locations corresponding to a digit on the display. Digit 0 is on the left side of the display and digit 7 is on the right side of the display. Address lines, A2-A0 select the digit address with A2 being the most significant bit and A0 being the least significant bit. The two types of data stored in the Character RAM are the ASCII coded data and the UDC Address Data. The type of data stored in the Character RAM is determined by data bit, D7. If D7 is low, then ASCII coded data is stored in data bits D6-D0. If D7 is high, then UDC Address Data is stored in data bit D3-D0. The ASCII coded data is a 7 bit code used to select one of 128 ASCII characters permanently stored in the ASCII ROM. The UDC Address data is a 4 bit code used to select one of the UDC characters in the UDC RAM. There are up to 16 characters available. See Figure 7. UDC Address Register and UDC RAM The UDC Address Register and UDC RAM allows the user to generate and store up to 16 custom characters. Each custom character is defined in 5 x 7 dot matrix pattern. It takes 8 write cycles to define a custom character, one cycle to load the UDC Address Register and 7 cycles to define the character. The contents of the UDC Address Register will store the 4 bit address for one of the 16 UDC RAM locations. The UDC RAM is used to store the custom character. Figure 7. Character RAM access logic RST 1 1 CE 0 0 WR 0 1 RD 1 0 FL 1 1 A4 1 1 A3 1 1 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 7 bit ASCII code, Write Cycle 0 7 bit ASCII code read during a Read Cycle
Character Address, Digits 0-7 Character Address, Digits 0-7
PDSP1880/1881/1882/1883/1884
2-115
tom character generation. UDC RAM The UDC RAM is selected by setting FL=1, A4=0, A3=1. The RAM is comprised of a 7 x 5 bit RAM. As shown in Figure 9, address lines, A2-A0 select one of the 7 rows of the custom character. Data bits, D4-D0 determine the 5 bits of column data in each row. Each data bit corresponds to a LED. If the data bit is high, then the LED is on. If the data bit is low, the LED is off. To create a character, each of the 7 rows of column data need to be defined. See Figures 8 for logic. Flash RAM The Flash RAM allows the display to flash one or more of the characters being displayed. The Flash Ram is accessed by setting FL low. A4 and A3 are ignored. The Flash RAM is a 8 x 1 bit RAM with each bit corresponding to a digit address. Digit 0 is on the left side of the display and digit 7 is on the right side of the display. Address lines, A2-A0 select the digit address with A2 being the most significant digit and A0 being the least significant digit. Data bit, D0, sets and resets the flash bit for each digit. When D0 is high, the flash bit is set and when D0 is low, it is reset. See Figure 9. Control Word The Control Word is used to set up the attributes required by the user. It is addressed by setting FL=1, A4=1, A3=0. The Control Word is an 8 bit register and is accessed using data bits, D7-D0. See Figures 10 and 11 for the logic and attributed control. The Control Word has 5 functions. They are brightness control, flashing character enable, blinking character enable, self test, and clear (Flash and Character RAMS only). Brightness Control Control Word bits, D2-D0, control the brightness of the display with a binary code of 000 being 100% brightness and 111 being display blank. See Figure 11 for brightness level versus binary code. The average ICC can be calculated by
multiplying the 100% brightness level ICC value by the display's brightness level. For example, a display set to 80% brightness with a 100% average ICC value of 200 mA will have an average ICC value of 200 mA x 80%=160 mA. Flash Function Control Word bit, D3, enables or disables the Flash Function. When D3 is 1, the Flash Function is enabled and any digit with its corresponding bit set in the Flash RAM will flash at approximately 2 hertz. When using an external clock, the flash rate can be determined by dividing the clock rate by 28,672. When D3 is 0, the Flash Function is disabled and the contents of the Flash RAM is ignored. For synchronized flashing on multiple displays, see the Reset Section. Blink Function Control Word bit, D4, enables or disables the Blink Function. When D4 is 1, the Blink Function is enabled and all characters on the display will blink at approximately 2 hertz. The Blink Function will override the Flash Function if both functions are enabled. When D4 is 0, the Blink Function is disabled. When using an external clock, the blink rate can be determined by dividing the clock rate by 28,672. For synchronized blinking on multiple displays, see the Reset Section. Self Test Before starting Self Test, Reset must first be activated. Control Word bits, D6 and D5, are used for the Self Test Function. When D6 is 1, the Self Test is initiated. Results of the Self Test are stored in bits D5. Control Word bit, D5, is a read only bit. When D5 is 1, Self Test passed is indicated. When D5 is 0, Self Test failed is indicated. The Self Test function of the IC consists of two internal routines which exercise major portions of the IC and illuminates all of the LEDs. The first routine cycles the ASCII decoder ROM through all states and performs a check sum on the output. If the check sum agrees with the correct value, D5 is set to a 1. The second routine provides a visual test of the LEDs using the drive circuitry. This is accomplished by writing checkered and inversed checkered patterns to the display. Each pattern is displayed for approximately 2 seconds. During the self test function the display must not be accessed. The time needed
Row Data
Column Data C1 C2 C3 C4 C5
A2 A1 A0 Row# 0 0 0 0 1 1 0 0 1 1 0 0 01 12 03 14 05 16
D4 D3 D2 D1 D0
5 x 7 Dot Matrix Pattern
11 07 to execute the self test function is calculated by multiplying the clock time by 262,144 (typical time4.6 sec.). At the end of the
PDSP1880/1881/1882/1883/1884
2-116
self test function, the Character RAM is loaded with blanks; the Control Word Register is set to zeroes except D5, and the Flash RAM is cleared and the UDC Address Register is set to all 1s. Figure 9. Flash RAM access logic RST 1 CE 0 WR 0 RD 1 FL 1 A4 X A3 X A2 A1 A0
RST 1
CE 0
WR 1
RD 1
FL 0
A4 X
A3 X
A2
A1
A0
Character Address, Digits 0-7
Figure 10. Control Word access logic D7 D6 D5 D4 D3 D2 D1 D0 RST CE WR RD FL A4 D0=Flash Data, 0=Flash Off and 0 0 1 1 1 1=Flash On (Write Cycle)
A3 0
A2
A1
A0
Flash RAM Ad1 dress, Digits 0-7
Not used for Control Word
RST 1
CE 0
WR 1
RD 0
FL 1
A4 1
A3 0
A2
A1
A0
D7 D6 D5 D4 D3 D2 D1 D0 Control Word data for a Read during a Read Cycle.
Not used for Control Word
Clear Function (see Figure 11 and Figure 12) Control Word bit, D7 clears the character RAM to 20 hex and the flash RAM to all zeroes. The RAMs are cleared within three clock cycles (110 s minimum, using the internal clock) when D7 is set to 1. During the clear time the display must not be accessed. When the clear function is finished, bit 7 of the Control Word RAM will be reset to a "0". Reset Function The display should be reset on power up of the display (RST=LOW). When the display is reset, the Character RAM, Flash RAM, and Control Word Register are cleared. The display's internal counters are reset. Reset cycle takes three clock cycles (110 seconds minimum using the internal clock). The display must not be accessed during this time. To synchronize the flashing and blinking of multiple displays, it is necessary for the display to use a common clock source and reset all the displays at the same time to start the internal counters at the same place. While RST is low, the display must not be accessed by RD nor WR. Figure 11. Control Word data definition Key D7 C D6 ST D5 ST D4 BL D3 FL D2 Br 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 X R D1 Br 0 0 1 1 0 0 1 1 D0 Br 0 1 0 1 0 0 0 1 100% Brightness 80% Brightness 53% Brightness 40% Brightness 27% Brightness 20% Brightness 13% Brightness Blank Display CClear function STSelf test BLBlink function FLFlash function BrBrightness control
Flash Function Disabled Flash Function Enabled
Blink Function Disabled Blink Function Enabled (overrides Flash Function)
Normal Operation X=bit ignored Run Self Test, R=Test Result, R=1/pass, 0=fail
Normal Operation Clear Flash RAM & Character RAM (Character RAM=20 Hex)
PDSP1880/1881/1882/1883/1884
2-117
Figure 12. Clear function CE 0 0 WR 0 1 FL 1 0 A3 0 0 A2 X X A1 X X A0 X X D7 0 1 D6 X X D5 X X D4 X X D3 X X D2 X X D1 X X D0 X X Operation Clear Disabled Clear User RAM, Flash RAM and Dispaly
PDSP1880/1881/1882/1883/1884
2-118
Figure 13. Display Cycle using built-in ROM example Display message "Showtime." Digit 0 is leftmost--Closest to Pin 1. Logic levels: 0=Low, 1=High, X=Don't care.
RST 0 1 1 1 1 1 1 1 1 1
ELECTRICAL AND MECHANICAL CONSIDERATIONS Voltage Transient Suppression
For best results power the display and the components that interface with the display to avoid logic inputs higher than VCC. Additionally, the LEDs may cause transients in the power supply lineD0 Operation CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 while they change display states. The Display common practice is to place a parallel combination of a .01 and a 22 X capacitor between VCC and GNDblank disF X 0 1 1 1 X X X X X X X X XF X X Reset. No Read/Write All for all witthin 3 Clock Cycles play packages.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0 0 0 0 0 0 0 0 0ESD Protection 1 0 0 1 1 53% Brightness Selected All blank
The0input protection structure of the PDSP188X provides sig0 1 1 Write "S" to Digit 0 S nificant protection against ESD damage. It is capable of withthe 0standing discharges greater thanDigit 1 Take allSH standard 1 0 0 0 Write "H" to 4 KV. precautions, normal for CMOS components. These include 0properly1 1 1 1 Write "O" to Digit 2 SHO grounding personnel, tools, tables, and transport carriers that come in contact with Digit 3 unshielded parts. If these 1 0 1 1 1 Write "W" to SHOW conditions are not, or cannot be met, keep the leads of the 1device shorted together or the parts in anti-static packaging. 0 1 0 0 Write "T" to Digit 4 SHOWT Refer to Appnote 18 in the current Siemens Optoelectronics 0 1 0 0 1 Write "I" to Digit 5 SHOWTI Data Book.
0Soldering Considerations "M" to Digit 6 1 1 0 1 Write SHOWTIM 0The0PDSP188X can be hand soldered7with SN63 solder 1 0 1 Write "E" to Digit SHOWTIME
using a grounded iron set to 260C. Figure 14. Displaying user defined character example Load character "A" into UDC-5 and then display it in digit 2 Logic levels: 0=Low, 1=High, X=Don't care.
RST 0 1 1 1 1 1 1 1 1 1 CE WR X 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 RD FL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 X 0 0 0 0 0 0 0 0 1 A3 X 0 1 1 1 1 1 1 1 1 A2 X X 0 0 0 0 1 1 1 0 A1 X X 0 0 1 1 0 0 1 1 A0 X X 0 1 0 1 0 1 0 0 D7 X X X X X X X X X 1 D6 X X X X X X X X X X D5 X X X X X X X X X X
Wave soldering is also possible following these conditions: Preheat that does not exceed 93C on the solder side of the PC board or a package surface temperature of 85C. Water soluble organic acid flux (except carboxylic acid) or resinbased RMA flux without alcohol can be used.
D4 D3 contact with alcohol or alcohol vapor will cause degraDisplay Direct D2 D1 D0 Operation
Wave temperature of 245C Cycles a dwell between 1.5 3 Clock 5C with sec. to 3.0 sec. Exposure to the wave should not exceed Xtemperatures0above 260C for five seconds at 0.063" below 0 1 1 Select UDC-5 All blank seating plane.0TheWrite into Row 1, UDC-5 be immersed in packages should not 0the 1 1 1 All blank the wave.
1
X
dation of the package.
X X X X
Reset. No Read/Write witthin All blank
Post Solder Cleaning Procedures
0
0
0
1
Write into Row 2, UDC-5
All blank
1The0least offensive cleaning solution is hot D.I. waterblank 0 0 1 Write into Row 3, UDC-5 All (60C) 1
for less than 15 minutes. Addition of mild saponifiers is 1 1 1 1 Write into Row 4, UDC-5 All blank acceptable. Do not use commercial diswasher detergents.
1For 0 0 0 1 Write into Row 5, UDC-5 All care faster cleaning, solvents may be used. Exercise blank in
X
choosing solvents1as some into Row 6, UDC-5attack the polymay chemically 0 0 0 Write All blank carbonate package. Maximum exposure should not exceed minutes at elevated temperatures.UDC-5 1two 0 0 0 1 Write into Row 7, Acceptable solvents All blank are TF (trichorotrifluorethane), and IPA.
1
Some major solvent manufacturers are: Allied Chemical Corportation, Specialty Chemical Division, Morristown, NJ; Baron-Blakeslee, Chicago, IL; Dow Chemical, Midland, MI; E.I. DuPont de Nemours & Co., Wilmington, DE. For further information refer to Appnote 19 in the current Siemens Optoelectronic Data Book (Display group1 in Table I applies). An alternative to soldering and cleaning the display modules is to use sockets. Naturally, 28 pin DIP sockets .300" wide
0
1
0
1
Write UDC-5 into Digit 2
(Digit2) A
PDSP1880/1881/1882/1883/1884
2-119

▲Up To Search▲

Price & Availability of PDSP1883

	To Download PDSP1883 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .